1. Field of the Invention
The present invention relates to an interface circuit for transferring signals and/or data, and particularly to an interface circuit for driving a signal/data bus line terminated in accordance with an active termination scheme. More particularly, the present invention relates to an interface circuit for transferring data of a semiconductor memory device at high speed.
2. Description of the Background Art
With progress of a semiconductor technology in recent years, operation frequencies of semiconductor chips have been remarkably improved. At present, central processing units (CPUs) operating in a GHz (giga hertz) class are available. For constituting a system, it is necessary to assemble various semiconductor devices such as a CPU and a semiconductor memory device on a motherboard, and to connect these semiconductor devices together via on-board interconnection lines. The on-board interconnection lines (wires) have larger interconnection widths and larger parasitic capacitances than interconnection lines inside the chip. Also, an on-board parasitic capacitance is present. Therefore, fast transfer of signal/data is difficult. Accordingly, the signal/data transfer only at a rate of about 100 MHz or lower can be achieved at the motherboard level. For this reason, a DDR (Double Data Rate) mode has been generally and widely used. In the DDR mode, data/signal is transferred in synchronization with both rising and falling edges of a transfer clock signal so that the signal/data is transferred at a doubled rate of the transfer clock signal.
Even in the signal/data transfer scheme according to the DDR mode, it has been attempted to achieve faster data/signal transfer by increasing the transfer frequency.
FIG. 44 shows by way of example a structure of a conventional memory system. In FIG. 44, the memory system includes memory units MU1 and MU2 as well as a chip set CH performing data access to these memory units MU1 and MU2. A data bus DB includes data bus lines DDBL for transmitting data DQ0-DQ63 of 64 bits and a strobe signal line SDBL for transferring a data strobe signal DQS providing strobe timing of data at chip set CH.
Memory units MU1 and MU2 are alternatively activated to transfer data of 4 bits. In this memory system, therefore, further memory units are connected to data bus DB, for transferring data of 60 bits. For the sake of simplicity, FIG. 44 representatively shows memory units MU1 and MU2 transferring data DQ0-DQ3 of 4 bits.
Each of memory units MU1 and MU2 is formed of a DIMM (Dual Inline Memory Module), in which memory chips are mounted on front and rear surfaces of a module substrate. In FIG. 44, opposite sides of each module substrate are represented by left and right sides L and R, respectively. Memory unit MU1 includes memory chips ML1-MLn mounted on a left side L1 and memory chips MR1-MRn mounted on a right side R1. Likewise, memory unit MU2 includes memory chips ML1-MLn mounted on a left side L2 and memory chips MR1-MRn mounted on a right side R2. Each of memory chips ML1-MLn and MR1-MRn sends and receives 4-bit data DQ0-DQ3 and data strobe signal DQS when selected.
When memory unit MU1 or MU2 transfers data to chip set CH, data strobe signal DQS is transferred in synchronization with the data to chip set CH from the memory chip sending the data.
Each of bus lines DDBL and SDBL of data bus DB is terminated with a termination voltage Vtt. This termination voltage is at a level of voltage VDDQ/2 intermediate between a power supply voltage VDDQ and a ground voltage. This termination voltage Vtt is supplied from a dedicated power supply circuit on the motherboard.
FIG. 45 is a signal waveform diagram illustrating an operation of transferring data from a memory unit in the memory system to the chip set shown in FIG. 44. Memory units MU1 and MU2 transfer data DQ in synchronization with rising and falling edges of a clock signal CLK when selected. For detecting the rising and falling edges of clock signal CLK, complementary clock signals CLK and /CLK are used, and the detection of the clock signal edges is performed within memory units MU1 and MU2 based on crossing portions of complementary clock signals CLK and /CLK.
Each of bus lines DDBL and SDBL of data bus DB is kept at termination voltage Vtt through a termination resistance in a standby state. By transferring data DQ in synchronization with the rising and falling edges of clock signal CLK, it is possible to transfer data at a double rate as compared to the Single Data Rate (SDR) mode, in which data is transferred in synchronization with only the rising or falling edge of the clock signal. Such fast data transfer makes the conditions of set-up and hold times of data severer. Data strobe signal DQS is used for accurately sampling the data by chip set CH.
This data strobe signal DQS indicates a position of the clock signal, where the data transfer is performed. The memory unit transferring data once sets data strobe signal DQS to L level before the data transfer, and thereafter toggles it between H- and L levels in synchronization with the clock signal for transferring data DQ in synchronization with data strobe signal DQS. Since data bus DB is terminated at termination voltage Vtt, the data transferring chip (memory chip or chip set) drives the data bus to H- or L level.
The bus topology shown in FIG. 44 has been generally used in a memory system including a DDR-SDRAM (Double Data Rate Synchronous DRAM). However, in order to feed the termination voltage Vtt, a chip dedicated to production of termination voltage Vtt must be arranged on the motherboard. Also, a termination resistance must be arranged for supplying the termination voltage Vtt to each of bus lines DDBL and SDBL of data bus DB. This termination resistance is formed of a pure resistance of a high resistance, and a considerable area on the motherboard is required for arranging the termination resistance to each bus line.
For overcoming the disadvantages of the bus termination scheme described above, an active termination scheme has been proposed.
FIG. 46 schematically shows a conventional system structure of an active termination scheme. FIG. 46 representatively shows a structure of a portion related to data bus line DDBL of one bit.
In each of memory units Mu1 and MU2, internal memory chips include output drive circuits ODK. Output drive circuit ODK is arranged as a final output stage in each memory chip. Data bus line DDBL is not connected to a termination resistance.
Chip set CH includes an output drive circuit ODK for driving data bus line DDBL for transferring output data, a differential amplifier circuit AMP1 for amplifying a difference between a signal on data bus line DDBL and a reference voltage Vref, a differential amplifier circuit AMP2 for amplifying a difference between a strobe signal STR and reference voltage Vref, and a latch circuit LKT for latching an output signal of differential amplifier circuit AMP1 in response to an output signal of differential amplifier circuit AMP2.
Latch circuit LKT includes a first latch entering a latch state when the output signal of differential amplifier circuit AMP2 is at an H level (logical high level), and a second latch entering a latch state when the output signal of differential amplifier circuit AMP2 is at an L level (logical low level). These first and second latches commonly receive the output signal of differential amplifier circuit AMP1. These first and second latches alternately operate to take in and latch the data, which are transferred in synchronization with the rising and falling of data strobe signal DQS. Differential amplifier circuits (AMP2) may be provided corresponding to each of the first and second latches for controlling operations of these latches. FIG. 46 shows a signal STR for representing that any one of the above structures may be employed. Strobe signal STR corresponds to data strobe signal DQS.
FIG. 47 schematically shows a structure of output drive circuit ODK shown in FIG. 46. In FIG. 47, output drive circuit ODK includes a P-channel MOS transistor DT1 which is connected between a power supply node and an output node ND and receives on its gate a pull-up control signal /DPU, an N-channel MOS transistor DT2 which is connected between output node ND and a ground node and receives on its gate a pull-down control signal DPD, resistance elements ZP and ZN each connected at one end to output node ND and having a high resistance, a P-channel MOS transistor TT1 connected between the power supply node and resistance element ZP and receiving on its gate a termination control signal/TRM, and an N-channel MOS transistor TT2 connected between resistance element ZN and the ground node and receiving on its gate a termination control signal TRM.
Control signals/DPU and DPD are produced in accordance with internal read data in a data output operation. Termination control signals/TRM and TRM are controlled on a memory unit basis. When a corresponding memory unit is selected, termination control signals TRM and /TRM turn inactive, and both MOS transistors TT1 and TT2 are kept in the off (non-conductive) state. When the corresponding memory unit is not selected, both termination control signals /TRM and TRM are kept active, and MOS transistors TT1 and TT2 are kept in the on (conductive) state.
According to the active termination scheme, termination of the bus is not made on the motherboard, but the termination of the bus signal line is made within the chip. For this termination within the chip, terminating resistances (pure resistances) ZP and ZN are formed in the chip, and termination control transistors TT1 and TT2 are arranged for controlling use/non-use of terminating resistances ZP and ZN.
FIG. 48 is a table listing on/off states of the transistors in the output drive circuit during the data transfer operation of the memory system shown in FIG. 46. FIG. 48 represents the states of the respective transistors in the case when output drive circuit ODK of the memory chip arranged on right side R2 of memory unit MU2 transfers the data to chip set CH.
When the data is to be transferred from the memory chip on right side R2 of memory unit MU2 to chip set CH, output transistors DT1 and DT2 are turned off in all output drive circuits ODK, except the output drive circuit ODK that transfers the data on right side R2 of memory unit MU2. In memory unit MU2, output transistors DT1 and DT2 in activated output drive circuit ODK are selectively driven to the on state in accordance with pull-up control signal/DPU and pull-down control signal DPD. In this output operation, output control signals/DPU and DPD are produced based on the internal read data so that one of output transistors DT1 and DT2 is kept on, and the other is kept off.
For the termination control, all termination control transistors TT1 and TT2 in selected memory unit MU2 are turned off, and all termination control transistors TT1 and TT2 are turned on in chip set CH and memory units MU1 other than memory unit MU2.
Thus, according to the termination control in this active termination scheme, the terminating operation is not stopped on the data sending side, and the termination control is performed by turning on termination control transistors TT1 and TT2 in the memory units other than that on the sending side and the chip set.
For sending data from chip set CH, e.g., to memory unit MU2, output transistors DT1 and DT2 in chip set CH are turned on/off in accordance with the data to be sent, and both termination control transistors TT1 and TT2 in chip set CH are turned off. In memory units MU1 and MU2, all termination control transistors TT1 and TT2 in the output drive circuits are turned on, and output transistors DT1 and DT2 are kept off.
As described above, the active termination scheme for terminating the bus does not require a termination resistance on the motherboard, and an area of the motherboard can be reduced. However, termination control transistors TT1 and TT2 are arranged on the final output stage in the chip. This results in a problem that an input capacitance of the data input/output node increases as described below.
Terminating resistances ZP and ZN are passive elements, and the termination control transistors must be connected thereto for actively controlling the terminating operations. The on resistance of the termination control transistor changes nonlinearly so that it is difficult to change linearly a supply current of this terminating resistance as well as a combined resistance value of the terminating resistance and the terminating controlling transistor. When terminating, MOS transistors TT1 and TT2 are in the on state, and a termination voltage is produced through the resistance division so that termination voltage Vtt deviates from the intermediate voltage level if the linearity is not achieved. Accordingly, such a structure is required that transistors of sufficiently large sizes are used for termination control transistors TT1 and TT2 with the on resistances thereof sufficiently reduced, to increase the linearity of the combined resistance value of terminating resistances ZP and ZN, for accurately setting the output voltage thereof to the intermediate voltage level.
For sufficiently lowering the on resistances of termination control transistors TT1 and TT2, termination control transistors TT1 and TT2 must have sizes similar to those of output transistors DT1 and DT2. This increases a parasitic capacitance by about 1 pF per data input/output node. If the data Input/output node has a capacitance of about 5 pF in a structure with output transistors D1 and D2 merely arranged as in a conventional output drive circuit, the capacitance of data input/output node increases to about 6 pF when the termination control transistors TT1 and TT2 are used. If the capacitance of data input/output node increases, the parasitic capacitance of the bus signal line increases so that fast charging and discharging of signal lines of the bus cannot be performed. Therefore, it is impossible to increase the transfer frequency for increasing the transfer rate.
FIG. 49 conceptually illustrates a relationship between an input capacitance and an operation frequency. In FIG. 49, the abscissa represents an input capacitance, and the ordinate represents an operation frequency. A curve represents a boundary between operative and nonoperative regions. As illustrated in FIG. 49, the operable frequency becomes low as the input capacitance increases, and becomes high as the input capacitance decreases.
With increase in input capacitance, the frequency region allowing a normal operation lowers, and fast data transfer is impeded. Further, a parasitic capacitance of a bus signal line (data bus line) increases, and therefore the charge/discharge current increases so that the current consumption disadvantageously increases.
If a termination control transistor of a size similar to that of an output drive transistor is arranged in the chip, a chip output stage disadvantageously occupies a large area.
An object of the invention is to provide an interface circuit and a semiconductor device, which can transfer data fast without increasing current consumption.
Another object of the invention is to provide an interface circuit and a semiconductor device, which can transfer data fast while suppressing increase in chip size.
Still another object of the invention is to provide an interface circuit, which can achieve a system capable of fast data transfer in an active termination scheme.
According to a first aspect of the invention, an interface circuit includes a first transistor for driving an output node to a first voltage level in accordance with an internal signal when the interface circuit is active, and being turned off when the interface circuit is inactive; and at least one second transistor being turned off when the interface circuit is active and the first transistor is on, and being selectively turned on to drive the output node to a second voltage level of a polarity different from that of the first voltage when the interface circuit is inactive.
According to a second aspect of the invention, an interface circuit includes a termination transistor coupled to an input node, and being turned on to drive the input node to a first power supply voltage level when a signal is applied to the input node; and an internal signal producing circuit for producing an internal signal in accordance with the signal applied to the input node. The input node is driven to a second power supply voltage level in accordance with the signal applied to the input node.
According to a third aspect of the invention, a semiconductor device includes a plurality of interface circuits commonly connected to an output node, each for selectively driving the output node to a first power supply voltage level in accordance with a corresponding internal signal when made active. The plurality of interface circuits is alternatively activated when the semiconductor device is selected. Each of the interface circuits includes an output drive transistor for driving the output node to the first power supply voltage level in accordance with the corresponding internal signal when the each interface circuit is active, and at least one termination transistor selectively turned on to drive the output node to a second power supply voltage level of a polarity different from that of the first power supply voltage when the each interface circuit is inactive.
In the interface circuit, data is transferred in an open drain method on the data sending side, and a bus signal line is terminated by a termination transistor at least on the receiving side. Therefore, it is not necessary to arrange a terminating resistance in a semiconductor chip, and a chip area can be reduced.
Since the output node is directly driven by the terminating transistor without using a termination resistance, the size of the terminating transistor can be made small, and a parasitic capacitance of the output node can be reduced. Therefore, data can be transferred fast with low current consumption. Also, an area occupied by the output circuit can be reduced.
Further, a power supply voltage is used as a terminating voltage, and it is not necessary to produce an intermediate voltage for termination. Therefore, the termination voltage at an intended voltage level can be accurately and stably produced even if the terminating transistor having non-linear operation characteristics is used. Since the linearity in on-resistance value is not required, transistors of small sizes can be used for terminating the signal lines of a bus.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.